The present invention is generally directed to a packaging configuration for integrated circuit chips which guarantees routability of interconnection lines and which may be rapidly configured in accordance with a given engineering design. More particularly, the present invention is related to a packaging method in which polymer film overlays are provided with metallization patterns as a means for configuring an integrated circuit chip or chips in an operating arrangement which is customized, yet may be produced in a very short time, typically less than one day. The packaging configuration of the present invention also permits the utilization of a novel macrocell chip design which is particularly useful for the testing of chip functional blocks.
The generic problem to be solved herein is the fabrication of an electronic system from a given engineering design in an economical and expeditious fashion. A second, related problem is providing a method of testing which quickly isolates faults and provides a very high degree of assurance that the tests have been thorough and complete. The testing method should be done in an expeditious and economical fashion. Clearly, electronic systems have coped with these problems to a degree. Prior art systems include: interconnections of packaged chips by wire wrap and printed circuit techniques, gate arrays, programmable logic arrays and fully customized integrated circuit fabrication. Interconnecting packaged chips has been the main method to provide many electronic systems over the past twenty years. In the wire wrap method, sockets with wire wraps are provided, and logic chips to be interconnected are placed in these sockets. Subsequently, interconnections are provided by wrapping wires around wire wrap pins according to a wire list. This can be done by automatic or manual machinery. The major drawback of wire wrap is the length of time required to wrap a single board, which precludes this method being economic for any but prototyping applications. In addition, wire wrap boards cannot be checked for accuracy of wiring both in interconnects and shorts except by using expensive, dedicated machinery. Also, wire wrap provides a relatively low performance interconnect since runs are long and since they suffer from high capacitance loading effects. Once chips have been installed on a wire wrap board, it is difficult to partition the board for simple tests, and so testing to a high degree of functional assurance generally requires complex and time consuming testing apparatus. Finally, wire wrap prototyping boards are expensive because they contain a large number of holes and each wire wrap socket must supply long pins for wire wrapping.
Printed circuit boards are another method of interconnecting packaged chips. A printed circuit board typically comprises copper runs adhered to a glass-fiber/epoxy substrate. Packaged chips are mounted on the substrate and package pins are soldered to runs on the board. In terms of prototyping, the time from completion of the circuit definition until populated boards are received can be quite long. Layout for the printed circuit boards, if done by hand, can require two weeks to a month for a fairly complicated circuit board containing 100-200 chips. Even with computer aided layout, the amount of computer time required to route the board is substantial for a complicated board. In addition, complicated boards require multiple circuit layers, which makes design and fabrication of a printed circuit board a time consuming process. A typical short turn around time can be on the order of two weeks. In addition, special tooling must be provided in order to test that all the connections are made on the board and that no undesired short circuits exist. At this point it is still necessary to populate the board with chips and to solder them in place. Chip population is generally done in different plant locations than board fabrication because a large number of chips must be kept in inventory and are specific to the needs of a particular operating department, while board fabrication is more generic in nature. The problem of testing the finished assembly is the same as with a wire wrap method in that a fully interconnected assembly generally requires a large array of complex test vectors in order to derive a high degree of assurance that the system will work under all desired conditions.
A gate array is also a solution to the problem of providing an electronic chip system. A gate array is primarily a medium to high volume device. In the gate array, arrays of P-channel and N-channel transistors are fabricated in an array structure on integrated circuit wafers. These circuits are completely fabricated with the exception of the last metallization step. Logic designs are achieved by custom connecting the P-channel and N-channel transistors with the last metallization layer. This method makes relatively efficient use of silicon and utilizes computer aided layout directly from circuit definitions. Time is required to fabricate masks for the last metallization step and to finish the processing of the wafers. Typically the steps of automatic layout mask generation and chip fabrication require at least two weeks. At this point, thousands of chips can be relatively easily fabricated, but thousands of chips are generally not required for prototyping quantities and for many applications. To further complicate the problem, complete systems require custom testing by the vendor of the gate array before the chips can be packaged with the test vectors and conditions developed and supplied by the circuit engineer. This means that the circuit engineer must do sufficient simulation to develop a set of qualification test vectors. Further testing must be accomplished after prototype chips arrive at the circuit engineer's site. While simulation can greatly decrease the risk of design errors in the chips, it does not cover the operation of a chip in an electronic system substantially similar to its operating environment. Generally, faults will be found and updates will be necessary and the requirement for additional prototypes with more changes will be created. This process is costly and stretches the time to completion of a project substantially because each iteration requires at least two weeks. In addition, a single gate array cannot provide all the structures necessary for a complete electronic system. For example, voltages and current may not be compatible at the interface level and may require addition of bipolar devices for analog digital conversion at the input and for digital to analog conversion at the output. Also, many systems require some form of memory. This means that the gate array would necessarily require an additional printed circuit board to interconnect the memory or interface devices.
A programmable logic array car be used to provide an electronic system economically in low volume for some applications. The major disadvantage of logic arrays is that they make inefficient use of silicon because the logic array must provide for all possible Boolean functions in "AND/OR" configurations. In those few applications where this type of Boolean logic is required the logic array can be programmed for the desired Boolean functions. Most systems, however, require a large number of logic arrays to achieve the desired function and this is not economical except possibly for the very first prototype.
Full custom integrated circuits can generally provide about two to three times the functionality available in the same area from a gate array, but the processing cost and non-recurring cost are substantially increased. Layout must now involve all layers of the chip and processing must also involve all layers of the chip. Three month turn-around times are typical for the processing associated with a fully custom integrated circuit chip. Test vectors and probe cards are also special. This means that substantial volume must be involved before the fully custom chip is economical. As a rule of thumb, volumes over 10,000 units per year are generally required.
The invention described herein also solves a slightly different problem with the same method and structure. In present day electronic systems, the primary components are usually readily available. These primary components include random access memory and microprocessor chip family sets as well as analog-to-digital and digital-to-analog conversion. In present day systems, these primary components are interconnected using TTL logic., As used herein, the term "TTL logic" or "TTL functions" refer to a set of functional blocks generally referred to as the 7400 series and described in the text "The TTL Data Book for Design Engineers" by Texas Instruments, Inc. This function of interconnecting, buffering and tying together the primary components of the system is generally referred to as a "glue logic function". For example, in present-day integrated circuit boards, one often finds certain standard functional chips surrounded by a plurality of custom interconnected integrated circuit chips in so-called DIP packages. It is these numerous small surrounding chips that provide a "glue function". In larger systems, the glue logic function may be provided by gate arrays and custom chips where a single chip replaces a large number of TTL chips. This leads to several problems. The first is that the number cf pins in the custom glue chip can be quite high. In addition, all of the primary components are immediately available. In the past, TTL was also immediately available and system interconnection could commence immediately on receipt of a given design. However, a time discontinuity now exists in which the primary components are available, but the custom glue logic takes many weeks to fabricate.
A problem solved by the invention in the parent patent application is defining a generic glue logic chip which can be used in place of a large number of conventional TTL logic chips. This glue logic chip is a multifunction digital circuit that includes a plurality of functional digital circuit blocks having input and output lines. Decoding means for selecting one of the functional blocks is also provided. Shift register means are also provided for storing test data and for storing output data from the output lines of the digital circuit blocks in response to test data presented. Such a multifunctional digit circuit may be repeated many times in a given integrated circuit package. Such a circuit is not only flexible, but is also readily testable both before and after customization.
The parent application describes how the fabrication of customized integrated circuit chips can be achieved with very fast turn around time by combining high density interconnect methods described in related patent documents (referred to below) with the novel glue logic integrated circuit. The integrated circuit is configured with a large number of small pads which are interconnected by the high density interconnect method. The chip is divided into a multiplicity of blocks which contain standard TTL functions such as latches, counters, gates, adders, etc. On-chip switches provide the ability to select a given logic function. A novel shift register circuit provides connections to all inputs and to all outputs on the chips for the purpose of testing. Testing can be accomplished both at the wafer level and uniquely at the system level where simple selection of switches can test any logic and any interconnects for opens and shorts. Blocks of logic elements and selection switches are iterated many times on a single chip. Using this configuration, a single chip which is 128 mils on a side, can replace the function of fifty logic chips and, additionally, provide capability for testing each separate logic block together with the capability for testing all system wiring for proper connection and freedom from short circuits.